This invention relates to a semiconductor device such as a semiconductor memory device, e.g. a dynamic random access memory (DRAM) device or a device including such semiconductor memory device. In particular, the present invention relates to a latency counter included in the semiconductor device.
A latency counter included in a DRAM device is proposed in an article entitled “A1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination” by Ho Young Song, et. al, ISSCC 2003/SESSION 17/SRAM AND DRAM/PAPER 17.8. The proposed latency counter is suitably operative at a higher frequency than another conventional latency counter mainly comprising a shift register.
However, the proposed latency control scheme requires two ring counters which dissipate large power.